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34 lines
787 B
Verilog
34 lines
787 B
Verilog
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module omsp_dbg_uart (dbg_clk, dbg_rst, mem_burst, cmd_valid);
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input dbg_clk;
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input dbg_rst;
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input mem_burst;
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output cmd_valid;
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reg [2:0] uart_state;
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reg [2:0] uart_state_nxt;
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wire xfer_done;
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parameter RX_SYNC = 3'h0;
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parameter RX_CMD = 3'h1;
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parameter RX_DATA = 3'h2;
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always @(uart_state or mem_burst)
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case (uart_state)
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RX_SYNC : uart_state_nxt = RX_CMD;
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RX_CMD : uart_state_nxt = mem_burst ? RX_DATA : RX_SYNC;
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RX_DATA : uart_state_nxt = RX_SYNC;
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default : uart_state_nxt = RX_CMD;
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endcase
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always @(posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) uart_state <= RX_SYNC;
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else if (xfer_done | mem_burst) uart_state <= uart_state_nxt;
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assign cmd_valid = (uart_state==RX_CMD) & xfer_done;
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assign xfer_done = uart_state!=RX_SYNC;
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endmodule
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