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116 lines
2.5 KiB
Verilog
116 lines
2.5 KiB
Verilog
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module mem2reg_test1(in_addr, in_data, out_addr, out_data);
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input [1:0] in_addr, out_addr;
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input [3:0] in_data;
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output reg [3:0] out_data;
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reg [3:0] array [2:0];
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always @* begin
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array[0] = 0;
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array[1] = 23;
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array[2] = 42;
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array[in_addr] = in_data;
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out_data = array[out_addr];
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end
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endmodule
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// ------------------------------------------------------
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module mem2reg_test2(clk, reset, mode, addr, data);
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input clk, reset, mode;
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input [2:0] addr;
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output [3:0] data;
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(* mem2reg *)
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reg [3:0] mem [0:7];
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assign data = mem[addr];
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integer i;
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always @(posedge clk) begin
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if (reset) begin
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for (i=0; i<8; i=i+1)
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mem[i] <= i;
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end else
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if (mode) begin
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for (i=0; i<8; i=i+1)
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mem[i] <= mem[i]+1;
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end else begin
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mem[addr] <= 0;
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end
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end
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endmodule
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// ------------------------------------------------------
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// http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
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module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
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reg [7:0] dint_c [0:7];
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always @(posedge clk)
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begin
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{dout_a[0], dint_c[3]} <= din_a;
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end
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assign dout_b = dint_c[3];
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endmodule
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// ------------------------------------------------------
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module mem2reg_test4(result1, result2, result3);
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output signed [9:0] result1;
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output signed [9:0] result2;
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output signed [9:0] result3;
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wire signed [9:0] intermediate [0:3];
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function integer depth2Index;
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input integer depth;
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depth2Index = depth;
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endfunction
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assign intermediate[depth2Index(1)] = 1;
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assign intermediate[depth2Index(2)] = 2;
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assign intermediate[3] = 3;
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assign result1 = intermediate[1];
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assign result2 = intermediate[depth2Index(2)];
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assign result3 = intermediate[depth2Index(3)];
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endmodule
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// ------------------------------------------------------
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module mem2reg_test5(input ctrl, output out);
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wire [0:0] foo[0:0];
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wire [0:0] bar[0:1];
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assign foo[0] = ctrl;
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assign bar[0] = 0, bar[1] = 1;
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assign out = bar[foo[0]];
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endmodule
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// ------------------------------------------------------
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module mem2reg_test6 (din, dout);
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input wire [3:0] din;
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output reg [3:0] dout;
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reg [1:0] din_array [1:0];
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reg [1:0] dout_array [1:0];
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always @* begin
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din_array[0] = din[0 +: 2];
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din_array[1] = din[2 +: 2];
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dout_array[0] = din_array[0];
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dout_array[1] = din_array[1];
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{dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0];
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dout[0 +: 2] = dout_array[0];
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dout[2 +: 2] = dout_array[1];
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end
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endmodule
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