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40 lines
1.1 KiB
Text
40 lines
1.1 KiB
Text
read_verilog ../../common/latches.v
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design -save read
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hierarchy -top latchp
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 3 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 3 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic
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cd latchsr # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT2
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select -assert-count 1 t:LUT4
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select -assert-count 5 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
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