mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
14 lines
215 B
Verilog
14 lines
215 B
Verilog
// Demo for assertpmux
|
|
|
|
module demo6 (input A, B, C, D, E, output reg Y);
|
|
always @* begin
|
|
Y = 0;
|
|
if (A != B) begin
|
|
(* parallel_case *)
|
|
case (C)
|
|
A: Y = D;
|
|
B: Y = E;
|
|
endcase
|
|
end
|
|
end
|
|
endmodule
|