Eddie Hung 295c18bd6b Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp		2019-08-30 09:50:20 -07:00
..
achronix	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
anlogic	Fix missing newline at end of file	2019-08-22 18:09:37 +02:00
common	Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp	2019-08-30 09:50:20 -07:00
coolrunner2	Fix spacing	2019-08-06 16:47:55 -07:00
easic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ecp5	Merge branch 'master' into xc7dsp	2019-08-30 13:57:15 +01:00
efinix	Fix missing newline at end of file	2019-08-22 18:06:36 +02:00
gowin	Fix formatting for msys2 mingw build using GetSize	2019-08-01 17:27:34 +02:00
greenpak4	techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module	2019-02-26 09:40:46 -08:00
ice40	Merge branch 'master' into xc7dsp	2019-08-30 13:57:15 +01:00
intel	techlibs/intel: Clean up Makefile	2019-08-05 11:22:11 -07:00
sf2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
xilinx	Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp	2019-08-30 09:50:20 -07:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00