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Code Activity
yosys/frontends
History
Emil J. Tywoniak 292d44f208 verilog: fix case location 
(cherry picked from commit 7713b5a811)
2026-06-24 15:15:13 +02:00
..
aiger aigerparse: better twines 2026-06-23 11:38:40 +02:00
aiger2 aiger2: fix twines 2026-06-23 16:00:43 +02:00
ast rtlil: replace SigSig actions with new type SyncAction 2026-06-24 15:14:53 +02:00
blif WIP migration to twine 2026-06-18 19:27:41 +02:00
json twine: fix replayability, reduce TwineSearch usage 2026-06-22 17:53:19 +02:00
liberty liberty: better twines 2026-06-23 11:38:48 +02:00
rpc WIP migration to twine 2026-06-18 19:27:41 +02:00
rtlil rtlil: replace SigSig actions with new type SyncAction 2026-06-24 15:14:53 +02:00
verific rtlil: set Module::design before name at all construction sites 2026-06-10 14:54:39 +02:00
verilog verilog: fix case location 2026-06-24 15:15:13 +02:00