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231 lines
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7.2 KiB
ReStructuredText
231 lines
No EOL
7.2 KiB
ReStructuredText
The extract pass
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----------------
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- Like the `techmap` pass, the `extract` pass is called with a map file. It
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compares the circuits inside the modules of the map file with the design and
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looks for sub-circuits in the design that match any of the modules in the map
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file.
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- If a match is found, the `extract` pass will replace the matching subcircuit
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with an instance of the module from the map file.
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- In a way the `extract` pass is the inverse of the techmap pass.
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.. todo:: add/expand supporting text, also mention custom pattern matching and
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pmgen
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Example code can be found in |code_examples/macc|_.
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.. |code_examples/macc| replace:: :file:`docs/source/code_examples/macc`
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.. _code_examples/macc: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/macc
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.. literalinclude:: /code_examples/macc/macc_simple_test.ys
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:language: yoscrypt
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:lines: 1-2
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.. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
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:class: width-helper invert-helper
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before `extract`
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.. literalinclude:: /code_examples/macc/macc_simple_test.ys
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:language: yoscrypt
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:lines: 6
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.. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
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:class: width-helper invert-helper
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after `extract`
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.. literalinclude:: /code_examples/macc/macc_simple_test.v
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:language: verilog
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:caption: :file:`macc_simple_test.v`
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.. literalinclude:: /code_examples/macc/macc_simple_xmap.v
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:language: verilog
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:caption: :file:`macc_simple_xmap.v`
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.. literalinclude:: /code_examples/macc/macc_simple_test_01.v
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:language: verilog
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:caption: :file:`macc_simple_test_01.v`
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.. figure:: /_images/code_examples/macc/macc_simple_test_01a.*
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:class: width-helper invert-helper
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.. figure:: /_images/code_examples/macc/macc_simple_test_01b.*
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:class: width-helper invert-helper
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.. literalinclude:: /code_examples/macc/macc_simple_test_02.v
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:language: verilog
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:caption: :file:`macc_simple_test_02.v`
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.. figure:: /_images/code_examples/macc/macc_simple_test_02a.*
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:class: width-helper invert-helper
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.. figure:: /_images/code_examples/macc/macc_simple_test_02b.*
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:class: width-helper invert-helper
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The wrap-extract-unwrap method
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Often a coarse-grain element has a constant bit-width, but can be used to
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implement operations with a smaller bit-width. For example, a 18x25-bit
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multiplier can also be used to implement 16x20-bit multiplication.
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A way of mapping such elements in coarse grain synthesis is the
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wrap-extract-unwrap method:
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wrap
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Identify candidate-cells in the circuit and wrap them in a cell with a
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constant wider bit-width using `techmap`. The wrappers use the same parameters
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as the original cell, so the information about the original width of the ports
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is preserved. Then use the `connwrappers` command to connect up the
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bit-extended in- and outputs of the wrapper cells.
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extract
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Now all operations are encoded using the same bit-width as the coarse grain
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element. The `extract` command can be used to replace circuits with cells of
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the target architecture.
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unwrap
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The remaining wrapper cell can be unwrapped using `techmap`.
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Example: DSP48_MACC
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~~~~~~~~~~~~~~~~~~~
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This section details an example that shows how to map MACC operations of
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arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder
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(such as the Xilinx DSP48 cells).
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Preconditioning: :file:`macc_xilinx_swap_map.v`
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Make sure ``A`` is the smaller port on all multipliers
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.. todo:: add/expand supporting text
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.. literalinclude:: /code_examples/macc/macc_xilinx_swap_map.v
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:language: verilog
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:caption: :file:`macc_xilinx_swap_map.v`
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Wrapping multipliers: :file:`macc_xilinx_wrap_map.v`
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.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
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:language: verilog
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:lines: 1-46
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:caption: :file:`macc_xilinx_wrap_map.v`
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Wrapping adders: :file:`macc_xilinx_wrap_map.v`
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.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
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:language: verilog
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:lines: 48-89
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:caption: :file:`macc_xilinx_wrap_map.v`
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Extract: :file:`macc_xilinx_xmap.v`
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.. literalinclude:: /code_examples/macc/macc_xilinx_xmap.v
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:language: verilog
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:caption: :file:`macc_xilinx_xmap.v`
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... simply use the same wrapping commands on this module as on the design to
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create a template for the `extract` command.
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Unwrapping multipliers: :file:`macc_xilinx_unwrap_map.v`
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.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
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:language: verilog
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:lines: 1-30
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:caption: ``$__mul_wrapper`` module in :file:`macc_xilinx_unwrap_map.v`
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Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
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.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
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:language: verilog
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:lines: 32-61
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:caption: ``$__add_wrapper`` module in :file:`macc_xilinx_unwrap_map.v`
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
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:language: verilog
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:lines: 1-6
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:caption: ``test1`` of :file:`macc_xilinx_test.v`
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.. figure:: /_images/code_examples/macc/macc_xilinx_test1a.*
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:class: width-helper invert-helper
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.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
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:class: width-helper invert-helper
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
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:language: verilog
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:lines: 8-13
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:caption: ``test2`` of :file:`macc_xilinx_test.v`
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2a.*
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:class: width-helper invert-helper
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
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:class: width-helper invert-helper
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Wrapping in ``test1``:
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.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
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:class: width-helper invert-helper
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
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:language: yoscrypt
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:start-after: part c
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:end-before: end part c
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.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
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:class: width-helper invert-helper
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Wrapping in ``test2``:
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
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:class: width-helper invert-helper
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
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:language: yoscrypt
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:start-after: part c
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:end-before: end part c
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
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:class: width-helper invert-helper
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Extract in ``test1``:
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.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
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:class: width-helper invert-helper
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
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:language: yoscrypt
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:start-after: part d
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:end-before: end part d
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.. figure:: /_images/code_examples/macc/macc_xilinx_test1d.*
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:class: width-helper invert-helper
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Extract in ``test2``:
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
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:class: width-helper invert-helper
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
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:language: yoscrypt
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:start-after: part d
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:end-before: end part d
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
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:class: width-helper invert-helper
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Unwrap in ``test2``:
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
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:class: width-helper invert-helper
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
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:language: yoscrypt
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:start-after: part e
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:end-before: end part e
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
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:class: width-helper invert-helper |