3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 13:10:51 +00:00
yosys/techlibs/anlogic
2022-01-19 08:51:25 +01:00
..
.gitignore
anlogic_eqn.cc
anlogic_fixcarry.cc
arith_map.v
brams.txt Removed dbits 8 since 9 will always be picked 2022-01-19 08:51:25 +01:00
brams_init.py
brams_map.v
cells_map.v
cells_sim.v
eagle_bb.v
lutram_init_16x4.vh
lutrams.txt
lutrams_map.v
Makefile.inc
synth_anlogic.cc