Marcelina Kościelnicka b98376884e test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. ... These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine.		2021-08-11 14:52:38 +02:00
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.gitignore
add_sub.ys
adffs.ys
bug1597.ys	Import tests from #1628	2020-01-27 13:56:16 -08:00
bug1598.ys
bug1626.ys	Add #1626 testcase	2020-01-12 15:21:26 -08:00
bug1644.il.gz	Add #1644 testcase	2020-01-17 15:57:52 -08:00
bug1644.ys	Add #1644 testcase	2020-01-17 15:57:52 -08:00
bug2061.ys	opt_lut: Allow more than one -dlogic per cell type.	2021-07-29 17:30:07 +02:00
counter.ys
dffs.ys
dpram.v
dpram.ys
fsm.ys	synth_ice40: Use opt_dff.	2020-07-30 22:26:20 +02:00
ice40_dsp.ys	test: ice40_dsp test to read +/ice40/cells_sim.v for default params	2020-04-22 16:35:35 -07:00
ice40_opt.ys	Import tests from #1628	2020-01-27 13:56:16 -08:00
ice40_wrapcarry.ys	Change attribute search value to specify precise location instead of simple line number.	2020-02-24 02:41:08 +00:00
latches.ys
logic.ys
macc.v
macc.ys
memories.ys	test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.	2021-08-11 14:52:38 +02:00
mul.ys
mux.ys	allow range for mux test	2020-06-01 13:48:19 +02:00
rom.v	Revert insertion of 'reg', leave note behind	2020-01-01 09:05:46 -08:00
rom.ys
run-test.sh	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
shifter.ys
tribuf.ys