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yosys/docs/source
KrystalDelusion 82888580ac
Merge pull request #5152 from garytwong/unique-if
verilog: implement SystemVerilog unique/unique0/priority if semantics.
2025-06-13 09:56:53 +12:00
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appendix docs: several small documentation fixes. 2025-05-29 21:26:28 -06:00
cell docs: mention related effects for multiplexers in the cell library. 2025-05-30 21:43:33 -06:00
code_examples Reinstate #4768 2025-04-08 11:58:05 +12:00
getting_started
using_yosys abc.rst: Clarify larger-but-slower 2025-05-31 09:10:27 +12:00
yosys_internals Merge pull request #5152 from garytwong/unique-if 2025-06-13 09:56:53 +12:00
bib.rst
cell_index.rst
cmd_ref.rst
conf.py Release version 0.54 2025-06-09 07:23:54 +02:00
index.rst
introduction.rst
literature.bib
requirements.txt