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yosys/techlibs/intel
2019-07-25 17:23:48 +02:00
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a10gx
common intel: Map M9K BRAM only on families that have it 2019-07-23 18:11:11 +01:00
cyclone10
cycloneiv
cycloneive Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
cyclonev Fixing issues in CycloneV cell sim 2019-04-11 19:59:03 -05:00
max10
Makefile.inc intel: Map M9K BRAM only on families that have it 2019-07-23 18:11:11 +01:00
synth_intel.cc Merge branch 'ZirconiumX-synth_intel_m9k' 2019-07-25 17:23:48 +02:00