mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
381 lines
No EOL
14 KiB
Python
381 lines
No EOL
14 KiB
Python
from itertools import chain
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import random
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def write_rtlil_cell(f, cell_type, inputs, outputs, parameters):
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f.write('autoidx 1\n')
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f.write('module \\gold\n')
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idx = 1
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for name, width in inputs.items():
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f.write(f'\twire width {width} input {idx} \\{name}\n')
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idx += 1
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for name, width in outputs.items():
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f.write(f'\twire width {width} output {idx} \\{name}\n')
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idx += 1
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f.write(f'\tcell ${cell_type} \\UUT\n')
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for (name, value) in parameters.items():
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if value >= 2**32:
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f.write(f'\t\tparameter \\{name} {value.bit_length()}\'{value:b}\n')
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else:
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f.write(f'\t\tparameter \\{name} {value}\n')
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for name in chain(inputs.keys(), outputs.keys()):
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f.write(f'\t\tconnect \\{name} \\{name}\n')
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f.write(f'\tend\nend\n')
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class BaseCell:
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def __init__(self, name, parameters, inputs, outputs, test_values):
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self.name = name
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self.parameters = parameters
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self.inputs = inputs
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self.outputs = outputs
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self.test_values = test_values
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def get_port_width(self, port, parameters):
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def parse_specifier(spec):
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if isinstance(spec, int):
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return spec
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if isinstance(spec, str):
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return parameters[spec]
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if callable(spec):
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return spec(parameters)
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assert False, "expected int, str or lambda"
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if port in self.inputs:
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return parse_specifier(self.inputs[port])
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elif port in self.outputs:
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return parse_specifier(self.outputs[port])
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else:
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assert False, "expected input or output"
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def generate_tests(self, rnd):
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def print_parameter(v):
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if isinstance(v, bool):
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return "S" if v else "U"
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else:
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return str(v)
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for values in self.test_values:
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if isinstance(values, int):
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values = [values]
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name = '-'.join([print_parameter(v) for v in values])
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parameters = {parameter: int(values[i]) for i, parameter in enumerate(self.parameters)}
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if self.is_test_valid(values):
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yield (name, parameters)
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def write_rtlil_file(self, path, parameters):
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inputs = {port: self.get_port_width(port, parameters) for port in self.inputs}
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outputs = {port: self.get_port_width(port, parameters) for port in self.outputs}
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with open(path, 'w') as f:
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write_rtlil_cell(f, self.name, inputs, outputs, parameters)
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def is_test_valid(self, values):
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return True
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class UnaryCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'Y_WIDTH', 'A_SIGNED'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
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class BinaryCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
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class ShiftCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
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def is_test_valid(self, values):
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(a_width, b_width, y_width, a_signed, b_signed) = values
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if not self.name in ('shift', 'shiftx') and b_signed: return False
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if self.name == 'shiftx' and a_signed: return False
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return True
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class MuxCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['WIDTH'], {'A': 'WIDTH', 'B': 'WIDTH', 'S': 1}, {'Y': 'WIDTH'}, values)
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class BWCell(BaseCell):
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def __init__(self, name, values):
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inputs = {'A': 'WIDTH', 'B': 'WIDTH'}
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if name == "bwmux": inputs['S'] = 'WIDTH'
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super().__init__(name, ['WIDTH'], inputs, {'Y': 'WIDTH'}, values)
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class PMuxCell(BaseCell):
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def __init__(self, name, values):
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b_width = lambda par: par['WIDTH'] * par['S_WIDTH']
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super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': 'WIDTH', 'B': b_width, 'S': 'S_WIDTH'}, {'Y': 'WIDTH'}, values)
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class BMuxCell(BaseCell):
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def __init__(self, name, values):
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a_width = lambda par: par['WIDTH'] << par['S_WIDTH']
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super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': a_width, 'S': 'S_WIDTH'}, {'Y': 'WIDTH'}, values)
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class DemuxCell(BaseCell):
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def __init__(self, name, values):
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y_width = lambda par: par['WIDTH'] << par['S_WIDTH']
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super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': 'WIDTH', 'S': 'S_WIDTH'}, {'Y': y_width}, values)
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class LUTCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['WIDTH', 'LUT'], {'A': 'WIDTH'}, {'Y': 1}, values)
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def generate_tests(self, rnd):
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for width in self.test_values:
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lut = rnd(f'lut-{width}').getrandbits(2**width)
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yield (f'{width}', {'WIDTH' : width, 'LUT' : lut})
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class ConcatCell(BaseCell):
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def __init__(self, name, values):
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y_width = lambda par: par['A_WIDTH'] + par['B_WIDTH']
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super().__init__(name, ['A_WIDTH', 'B_WIDTH'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': y_width}, values)
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class SliceCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'OFFSET', 'Y_WIDTH'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
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class FACell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['WIDTH'], {'A': 'WIDTH', 'B': 'WIDTH', 'C': 'WIDTH'}, {'X': 'WIDTH', 'Y': 'WIDTH'}, values)
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self.sim_preprocessing = "techmap" # because FA is not implemented in yosys sim
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class LCUCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['WIDTH'], {'P': 'WIDTH', 'G': 'WIDTH', 'CI': 1}, {'CO': 'WIDTH'}, values)
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self.sim_preprocessing = "techmap" # because LCU is not implemented in yosys sim
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class ALUCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH', 'CI': 1, 'BI': 1}, {'X': 'Y_WIDTH', 'Y': 'Y_WIDTH', 'CO': 'Y_WIDTH'}, values)
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self.sim_preprocessing = "techmap" # because ALU is not implemented in yosys sim
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class FailCell(BaseCell):
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def __init__(self, name):
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super().__init__(name, [], {}, {})
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def generate_tests(self, rnd):
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yield ('', {})
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def write_rtlil_file(self, path, parameters):
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raise Exception(f'\'{self.name}\' cell unimplemented in test generator')
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class FFCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['WIDTH'], ['D'], ['Q'], values)
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def write_rtlil_file(self, path, parameters):
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from test_functional import yosys_synth
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verilog_file = path.parent / 'verilog.v'
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with open(verilog_file, 'w') as f:
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width = parameters['WIDTH']
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f.write(f"""
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module gold(
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input wire clk,
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input wire [{width-1}:0] D,
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output reg [{width-1}:0] Q
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);
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initial Q = {width}'b{("101" * width)[:width]};
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always @(posedge clk)
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Q <= D;
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endmodule""")
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yosys_synth(verilog_file, path)
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class MemCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['DATA_WIDTH', 'ADDR_WIDTH'], {'WA': 'ADDR_WIDTH', 'RA': 'ADDR_WIDTH', 'WD': 'DATA_WIDTH'}, {'RD': 'DATA_WIDTH'}, values)
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def write_rtlil_file(self, path, parameters):
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from test_functional import yosys_synth
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verilog_file = path.parent / 'verilog.v'
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with open(verilog_file, 'w') as f:
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f.write("""
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module gold(
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input wire clk,
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input wire [{1}:0] WA,
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input wire [{0}:0] WD,
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input wire [{1}:0] RA,
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output reg [{0}:0] RD
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);
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reg [{0}:0] mem[0:{2}];
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integer i;
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initial
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for(i = 0; i <= {2}; i = i + 1)
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mem[i] = 9192 * (i + 1);
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always @(*)
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RD = mem[RA];
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always @(posedge clk)
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mem[WA] <= WD;
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endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1, 2**parameters['ADDR_WIDTH'] - 1))
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yosys_synth(verilog_file, path)
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class MemDualCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['DATA_WIDTH', 'ADDR_WIDTH'],
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{'WA1': 'ADDR_WIDTH', 'WA2': 'ADDR_WIDTH',
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'RA1': 'ADDR_WIDTH', 'RA2': 'ADDR_WIDTH',
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'WD1': 'DATA_WIDTH', 'WD2': 'DATA_WIDTH'},
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{'RD1': 'DATA_WIDTH', 'RD2': 'DATA_WIDTH'}, values)
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self.sim_preprocessing = "memory_map" # issue #4496 in yosys -sim prevents this example from working without memory_map
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def write_rtlil_file(self, path, parameters):
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from test_functional import yosys_synth
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verilog_file = path.parent / 'verilog.v'
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with open(verilog_file, 'w') as f:
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f.write("""
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module gold(
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input wire clk,
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input wire [{1}:0] WA1,
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input wire [{0}:0] WD1,
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input wire [{1}:0] WA2,
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input wire [{0}:0] WD2,
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input wire [{1}:0] RA1,
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input wire [{1}:0] RA2,
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output reg [{0}:0] RD1,
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output reg [{0}:0] RD2
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);
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reg [{0}:0] mem[0:{2}];
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integer i;
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initial
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for(i = 0; i <= {2}; i = i + 1)
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mem[i] = 9192 * (i + 1);
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always @(*)
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RD1 = mem[RA1];
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always @(*)
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RD2 = mem[RA2];
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always @(posedge clk) begin
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mem[WA1] <= WD1;
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mem[WA2] <= WD2;
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end
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endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1, 2**parameters['ADDR_WIDTH'] - 1))
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yosys_synth(verilog_file, path)
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class PicorvCell(BaseCell):
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def __init__(self):
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super().__init__("picorv", [], {}, {}, [()])
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self.smt_max_steps = 50 # z3 is too slow for more steps
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def write_rtlil_file(self, path, parameters):
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from test_functional import yosys, base_path, quote
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tb_file = base_path / 'tests/functional/picorv32_tb.v'
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cpu_file = base_path / 'tests/functional/picorv32.v'
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yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; write_rtlil {quote(path)}")
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binary_widths = [
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# try to cover extending A operand, extending B operand, extending/truncating result
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(16, 32, 48, True, True),
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(16, 32, 48, False, False),
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(32, 16, 48, True, True),
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(32, 16, 48, False, False),
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(32, 32, 16, True, True),
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(32, 32, 16, False, False),
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# have at least one test that checks small inputs, which will exercise the cornercases more
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(4, 4, 8, True, True),
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(4, 4, 8, False, False)
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]
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unary_widths = [
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(6, 12, True),
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(6, 12, False),
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(32, 16, True),
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(32, 16, False)
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]
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# note that meaningless combinations of signednesses are eliminated,
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# like e.g. most shift operations don't take signed shift amounts
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shift_widths = [
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# one set of tests that definitely checks all possible shift amounts
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# with a bigger result width to make sure it's not truncated
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(32, 6, 64, True, False),
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(32, 6, 64, False, False),
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(32, 6, 64, True, True),
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(32, 6, 64, False, True),
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# one set that checks very oversized shifts
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(32, 32, 64, True, False),
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(32, 32, 64, False, False),
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(32, 32, 64, True, True),
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(32, 32, 64, False, True),
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# at least one test where the result is going to be truncated
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(32, 6, 16, False, False),
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# since 1-bit shifts are special cased
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(1, 4, 1, False, False),
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(1, 4, 1, True, False),
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]
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rtlil_cells = [
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UnaryCell("not", unary_widths),
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UnaryCell("pos", unary_widths),
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UnaryCell("neg", unary_widths),
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BinaryCell("and", binary_widths),
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BinaryCell("or", binary_widths),
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BinaryCell("xor", binary_widths),
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BinaryCell("xnor", binary_widths),
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UnaryCell("reduce_and", unary_widths),
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UnaryCell("reduce_or", unary_widths),
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UnaryCell("reduce_xor", unary_widths),
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UnaryCell("reduce_xnor", unary_widths),
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UnaryCell("reduce_bool", unary_widths),
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ShiftCell("shl", shift_widths),
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ShiftCell("shr", shift_widths),
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ShiftCell("sshl", shift_widths),
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ShiftCell("sshr", shift_widths),
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ShiftCell("shift", shift_widths),
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ShiftCell("shiftx", shift_widths),
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FACell("fa", [8, 20]),
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LCUCell("lcu", [1, 10]),
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ALUCell("alu", binary_widths),
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BinaryCell("lt", binary_widths),
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BinaryCell("le", binary_widths),
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BinaryCell("eq", binary_widths),
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BinaryCell("ne", binary_widths),
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BinaryCell("eqx", binary_widths),
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BinaryCell("nex", binary_widths),
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BinaryCell("ge", binary_widths),
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BinaryCell("gt", binary_widths),
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BinaryCell("add", binary_widths),
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BinaryCell("sub", binary_widths),
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BinaryCell("mul", binary_widths),
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# BinaryCell("macc"),
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BinaryCell("div", binary_widths),
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BinaryCell("mod", binary_widths),
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BinaryCell("divfloor", binary_widths),
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BinaryCell("modfloor", binary_widths),
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BinaryCell("pow", binary_widths),
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UnaryCell("logic_not", unary_widths),
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BinaryCell("logic_and", binary_widths),
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BinaryCell("logic_or", binary_widths),
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SliceCell("slice", [(32, 10, 15), (8, 0, 4), (10, 0, 10)]),
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ConcatCell("concat", [(16, 16), (8, 14), (20, 10)]),
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MuxCell("mux", [10, 16, 40]),
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BMuxCell("bmux", [(10, 1), (10, 2), (10, 4)]),
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PMuxCell("pmux", [(10, 1), (10, 4), (20, 4)]),
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DemuxCell("demux", [(10, 1), (32, 2), (16, 4)]),
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LUTCell("lut", [4, 6, 8]),
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# ("sop", ["A", "Y"]),
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# ("tribuf", ["A", "EN", "Y"]),
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# ("specify2", ["EN", "SRC", "DST"]),
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# ("specify3", ["EN", "SRC", "DST", "DAT"]),
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# ("specrule", ["EN_SRC", "EN_DST", "SRC", "DST"]),
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BWCell("bweqx", [10, 16, 40]),
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BWCell("bwmux", [10, 16, 40]),
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FFCell("ff", [10, 20, 40]),
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MemCell("mem", [(16, 4)]),
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MemDualCell("mem-dual", [(16, 4)]),
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# ("assert", ["A", "EN"]),
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# ("assume", ["A", "EN"]),
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# ("live", ["A", "EN"]),
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# ("fair", ["A", "EN"]),
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# ("cover", ["A", "EN"]),
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# ("initstate", ["Y"]),
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# ("anyconst", ["Y"]),
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# ("anyseq", ["Y"]),
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# ("anyinit", ["D", "Q"]),
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# ("allconst", ["Y"]),
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# ("allseq", ["Y"]),
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# ("equiv", ["A", "B", "Y"]),
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# ("print", ["EN", "TRG", "ARGS"]),
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# ("check", ["A", "EN", "TRG", "ARGS"]),
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# ("set_tag", ["A", "SET", "CLR", "Y"]),
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# ("get_tag", ["A", "Y"]),
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# ("overwrite_tag", ["A", "SET", "CLR"]),
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# ("original_tag", ["A", "Y"]),
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# ("future_ff", ["A", "Y"]),
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# ("scopeinfo", []),
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PicorvCell()
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]
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def generate_test_cases(per_cell, rnd):
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tests = []
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names = []
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for cell in rtlil_cells:
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seen_names = set()
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for (name, parameters) in cell.generate_tests(rnd):
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if not name in seen_names:
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seen_names.add(name)
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tests.append((cell, parameters))
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names.append(f'{cell.name}-{name}' if name != '' else cell.name)
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if per_cell is not None and len(seen_names) >= per_cell:
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break
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return (names, tests) |