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62 lines
1.2 KiB
Verilog
62 lines
1.2 KiB
Verilog
module gold(
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input wire clk,
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output reg resetn,
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output wire trap,
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output wire mem_valid,
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output wire mem_instr,
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output wire mem_ready,
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output wire [31:0] mem_addr,
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output wire [31:0] mem_wdata,
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output wire [31:0] mem_wstrb,
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output wire [31:0] mem_rdata,
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);
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initial resetn = 1'b0;
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always @(posedge clk) resetn <= 1'b1;
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reg [31:0] rom[0:15];
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initial begin
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rom[0] = 32'h00200093;
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rom[1] = 32'h00200113;
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rom[2] = 32'h00111863;
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rom[3] = 32'h00102023;
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rom[4] = 32'h00108093;
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rom[5] = 32'hfe0008e3;
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rom[6] = 32'h00008193;
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rom[7] = 32'h402181b3;
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rom[8] = 32'hfe304ee3;
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rom[9] = 32'hfe0186e3;
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rom[10] = 32'h00110113;
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rom[11] = 32'hfc000ee3;
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end
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assign mem_ready = 1'b1;
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assign mem_rdata = rom[mem_addr[5:2]];
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wire pcpi_wr = 1'b0;
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wire [31:0] pcpi_rd = 32'b0;
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wire pcpi_wait = 1'b0;
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wire pcpi_ready = 1'b0;
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wire [31:0] irq = 32'b0;
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picorv32 picorv32_i(
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.clk(clk),
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.resetn(resetn),
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.trap(trap),
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.mem_valid(mem_valid),
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.mem_instr(mem_instr),
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.mem_ready(mem_ready),
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.mem_addr(mem_addr),
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.mem_wdata(mem_wdata),
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.mem_wstrb(mem_wstrb),
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.mem_rdata(mem_rdata),
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.pcpi_wr(pcpi_wr),
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.pcpi_rd(pcpi_rd),
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.pcpi_wait(pcpi_wait),
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.pcpi_ready(pcpi_ready),
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.irq(irq)
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);
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endmodule
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