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19 lines
272 B
Systemverilog
19 lines
272 B
Systemverilog
module top (
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input clk, rst,
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output reg [3:0] cnt
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);
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initial cnt = 0;
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always @(posedge clk) begin
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if (rst)
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cnt <= 0;
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else
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cnt <= cnt + 4'd 1;
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end
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always @(posedge clk) begin
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assume (cnt != 10);
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assert (cnt != 15);
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end
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endmodule
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