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yosys/techlibs/ice40
2019-05-21 14:21:00 -07:00
..
tests
.gitignore
abc_hx.box Make SB_DFF whitebox 2019-04-19 08:36:38 -07:00
abc_hx.lut Fix rename 2019-04-18 09:04:34 -07:00
abc_lp.box Make SB_DFF whitebox 2019-04-19 08:36:38 -07:00
abc_lp.lut Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
abc_u.box Make SB_DFF whitebox 2019-04-19 08:36:38 -07:00
abc_u.lut Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
arith_map.v Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" 2019-04-17 11:10:20 -07:00
brams.txt
brams_init.py
brams_map.v ice40: use 2 bits for READ/WRITE MODE for SB_RAM map 2019-02-28 16:23:40 -08:00
cells_map.v Map to SB_LUT4 from fastest input first 2019-04-17 13:01:17 -07:00
cells_sim.v Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-21 14:21:00 -07:00
ice40_braminit.cc Fix typo in ice40_braminit help msg 2019-03-09 13:24:55 -08:00
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" 2019-04-17 11:10:20 -07:00
ice40_unlut.cc
latches_map.v
Makefile.inc Also update Makefile.inc 2019-04-18 09:58:34 -07:00
synth_ice40.cc Merge pull request #969 from YosysHQ/clifford/pmgenstuff 2019-05-03 20:39:50 +02:00