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27377c4663
Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present.
101 lines
1.2 KiB
Verilog
101 lines
1.2 KiB
Verilog
module mux2 (S,A,B,Y);
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input S;
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input A,B;
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output reg Y;
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always @(*)
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Y = (S)? B : A;
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endmodule
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module mux4 ( S, D, Y );
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input[1:0] S;
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input[3:0] D;
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output Y;
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reg Y;
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wire[1:0] S;
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wire[3:0] D;
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always @*
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begin
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case( S )
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0 : Y = D[0];
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1 : Y = D[1];
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2 : Y = D[2];
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3 : Y = D[3];
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endcase
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end
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endmodule
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module mux8 ( S, D, Y );
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input[2:0] S;
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input[7:0] D;
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output Y;
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reg Y;
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wire[2:0] S;
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wire[7:0] D;
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always @*
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begin
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case( S )
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0 : Y = D[0];
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1 : Y = D[1];
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2 : Y = D[2];
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3 : Y = D[3];
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4 : Y = D[4];
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5 : Y = D[5];
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6 : Y = D[6];
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7 : Y = D[7];
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endcase
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end
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endmodule
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module mux16 (D, S, Y);
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input [15:0] D;
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input [3:0] S;
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output Y;
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assign Y = D[S];
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endmodule
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module top (
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input [3:0] S,
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input [15:0] D,
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output M2,M4,M8,M16
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);
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mux2 u_mux2 (
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.S (S[0]),
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.A (D[0]),
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.B (D[1]),
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.Y (M2)
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);
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mux4 u_mux4 (
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.S (S[1:0]),
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.D (D[3:0]),
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.Y (M4)
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);
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mux8 u_mux8 (
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.S (S[2:0]),
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.D (D[7:0]),
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.Y (M8)
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);
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mux16 u_mux16 (
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.S (S[3:0]),
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.D (D[15:0]),
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.Y (M16)
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);
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endmodule
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