mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-11 11:43:38 +00:00
27377c4663
Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present.
15 lines
658 B
Plaintext
15 lines
658 B
Plaintext
read_verilog fsm.v
|
|
hierarchy -top top
|
|
proc
|
|
flatten
|
|
#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
|
|
#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
|
|
equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd top # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:AL_MAP_LUT2
|
|
select -assert-count 5 t:AL_MAP_LUT5
|
|
select -assert-count 1 t:AL_MAP_LUT6
|
|
select -assert-count 6 t:AL_MAP_SEQ
|
|
select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
|