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45 lines
706 B
Text
45 lines
706 B
Text
# Regression test for #3467
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read_verilog <<EOT
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module bit_buf (
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input wire bit_in,
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output wire bit_out
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);
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assign bit_out = bit_in;
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endmodule
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module top (
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input wire [3:0] data_in,
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output wire [3:0] data_out
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);
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wire [3:0] data [0:4];
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assign data[0] = data_in;
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assign data_out = data[4];
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genvar i;
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generate
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for (i=0; i<=3; i=i+1) begin
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bit_buf bit_buf_instance[3:0] (
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.bit_in(data[i]),
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.bit_out(data[i + 1])
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);
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end
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endgenerate
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endmodule
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module top2 (
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input wire [3:0] data_in,
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output wire [3:0] data_out
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);
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assign data_out = data_in;
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endmodule
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EOT
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hierarchy
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proc
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miter -equiv -make_assert -flatten top top2 miter
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sat -prove-asserts -verify miter
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