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17 lines
291 B
Verilog
17 lines
291 B
Verilog
module test1(in_addr, in_data, out_addr, out_data);
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input [1:0] in_addr, out_addr;
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input [3:0] in_data;
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output reg [3:0] out_data;
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reg [3:0] array [2:0];
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always @* begin
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array[0] = 0;
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array[1] = 23;
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array[2] = 42;
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array[in_addr] = in_data;
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out_data = array[out_addr];
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end
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endmodule
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