mirror of
https://github.com/YosysHQ/yosys
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160 lines
5 KiB
Verilog
160 lines
5 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Simple Baud Rate Generator ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/sasc/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: sasc_brg.v,v 1.2 2002/11/08 15:22:49 rudi Exp $
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//
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// $Date: 2002/11/08 15:22:49 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: sasc_brg.v,v $
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// Revision 1.2 2002/11/08 15:22:49 rudi
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//
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// Fixed a typo in brg
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//
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// Revision 1.1.1.1 2002/09/16 16:16:40 rudi
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// Initial Checkin
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//
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//
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//
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//
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//
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//
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//
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//
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`include "timescale.v"
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/*
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Baud rate Generator
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==================
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div0 - is the first stage divider
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Set this to the desired number of cycles less two
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div1 - is the second stage divider
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Set this to the actual number of cycles
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Remember you have to generate a baud rate that is 4 higher than what
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you really want. This is because of the DPLL in the RX section ...
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Example:
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If your system clock is 50MHz and you want to generate a 9.6 Kbps baud rate:
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9600*4 = 38400KHz
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50MHz/38400KHz=1302 or 6*217
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set div0=4 (6-2) and set div1=217
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*/
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module sasc_brg(clk, rst, div0, div1, sio_ce, sio_ce_x4);
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input clk;
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input rst;
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input [7:0] div0, div1;
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output sio_ce, sio_ce_x4;
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///////////////////////////////////////////////////////////////////
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//
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// Local Wires and Registers
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//
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reg [7:0] ps;
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reg ps_clr;
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reg [7:0] br_cnt;
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reg br_clr;
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reg sio_ce_x4_r;
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reg [1:0] cnt;
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reg sio_ce, sio_ce_x4;
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reg sio_ce_r ;
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reg sio_ce_x4_t;
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///////////////////////////////////////////////////////////////////
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//
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// Boud Rate Generator
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//
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// -----------------------------------------------------
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// Prescaler
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always @(posedge clk)
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if(!rst) ps <= #1 8'h0;
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else
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if(ps_clr) ps <= #1 8'h0;
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else ps <= #1 ps + 8'h1;
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always @(posedge clk)
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ps_clr <= #1 (ps == div0); // Desired number of cycles less 2
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// -----------------------------------------------------
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// Oversampled Boud Rate (x4)
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always @(posedge clk)
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if(!rst) br_cnt <= #1 8'h0;
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else
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if(br_clr) br_cnt <= #1 8'h0;
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else
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if(ps_clr) br_cnt <= #1 br_cnt + 8'h1;
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always @(posedge clk)
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br_clr <= #1 (br_cnt == div1); // Prciese number of PS cycles
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always @(posedge clk)
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sio_ce_x4_r <= #1 br_clr;
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always @(posedge clk)
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sio_ce_x4_t <= #1 !sio_ce_x4_r & br_clr;
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always @(posedge clk)
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sio_ce_x4 <= #1 sio_ce_x4_t;
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// -----------------------------------------------------
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// Actual Boud rate
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always @(posedge clk)
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if(!rst) cnt <= #1 2'h0;
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else
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if(!sio_ce_x4_r & br_clr) cnt <= #1 cnt + 2'h1;
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always @(posedge clk)
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sio_ce_r <= #1 (cnt == 2'h0);
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always @(posedge clk)
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sio_ce <= #1 !sio_ce_r & (cnt == 2'h0);
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endmodule
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