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yosys/backends
Miodrag Milanović 8180cc4325
Merge pull request #3624 from jix/sim_yw
Changes to support SBY trace generation with the sim command
2023-01-23 16:55:17 +01:00
..
aiger sim: Improvements and fixes for yw cosim 2023-01-11 18:07:16 +01:00
blif
btor sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
cxxrtl
edif
firrtl Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
intersynth
jny Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
json Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
rtlil Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
simplec
smt2 sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
smv Add bwmuxmap pass 2022-11-30 18:50:53 +01:00
spice
table
verilog Add bwmuxmap pass 2022-11-30 18:50:53 +01:00