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67b4ce06e0
This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
34 lines
518 B
Plaintext
34 lines
518 B
Plaintext
bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
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init 1
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abits 13 @M1
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dbits 1 @M1
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abits 12 @M2
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dbits 2 @M2
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abits 11 @M3
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dbits 4 @M3
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abits 10 @M4
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dbits 8 @M4
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abits 10 @M5
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dbits 9 @M5
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abits 9 @M6
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dbits 16 @M6
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abits 9 @M7
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dbits 18 @M7
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abits 8 @M8
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dbits 32 @M8
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abits 8 @M9
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dbits 36 @M9
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
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min efficiency 2
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make_transp
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endmatch
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