yosys/tests/verilog/func_tern_hint.ys at 26a6c604788f947df5142088224b1989320ba467 - mirrors/yosys - Libre-Chip.org

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Zachary Snow a650d9079f verilog: fix width/sign detection for functions

2022-05-30 16:45:39 -04:00

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 read_verilog -sv func_tern_hint.sv
 proc
 opt
 sat -verify -seq 1 -prove-asserts -show-all