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yosys/techlibs/common
2026-06-25 04:51:46 -07:00
..
choices Merge pull request #4789 from YosysHQ/emil/sklansky-adder 2024-12-03 11:33:13 +01:00
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py simcells: Apply group tags 2024-10-15 07:35:40 +13:00
mul2dsp.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
opensta.cc Migrate build system to CMake 2026-06-03 08:58:10 +00:00
opensta.h opensta: refactor default command 2025-11-19 15:20:50 +01:00
pmux2mux.v
prep.cc Undo the terrible upstream changes that break everything... 2026-02-04 22:26:06 -08:00
sdc_expand.cc opensta, sdc_expand: mark as experimental 2025-11-19 15:31:17 +01:00
simcells.v simcells: $dffsr and derivatives undefine S&R in logic tables 2026-03-19 19:27:30 +01:00
simlib.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
smtmap.v
synth.cc Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00
techmap.v simplemap: Moves $pmux mapping from techmap.v to simple map 2026-04-29 21:20:39 +00:00