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50 lines
1.5 KiB
Text
50 lines
1.5 KiB
Text
# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
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# w4b | r16b
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design -reset
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read_verilog asym_ram_sdp_read_wider.v
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synth_xilinx -top asym_ram_sdp_read_wider -noiopad
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select -assert-count 1 t:RAMB18E1
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# w8b | r16b
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design -reset
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read_verilog asym_ram_sdp_read_wider.v
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chparam -set WIDTHA 8 -set SIZEA 512 -set ADDRWIDTHA 9 asym_ram_sdp_read_wider
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synth_xilinx -top asym_ram_sdp_read_wider -noiopad
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select -assert-count 1 t:RAMB18E1
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# w4b | r32b
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design -reset
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read_verilog asym_ram_sdp_read_wider.v
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chparam -set WIDTHB 32 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
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synth_xilinx -top asym_ram_sdp_read_wider -noiopad
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select -assert-count 1 t:RAMB18E1
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# w16b | r4b
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design -reset
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read_verilog asym_ram_sdp_write_wider.v
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synth_xilinx -top asym_ram_sdp_write_wider -noiopad
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select -assert-count 1 t:RAMB18E1
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# w16b | r8b
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design -reset
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read_verilog asym_ram_sdp_write_wider.v
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chparam -set WIDTHB 8 -set SIZEB 512 -set ADDRWIDTHB 9 asym_ram_sdp_read_wider
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synth_xilinx -top asym_ram_sdp_write_wider -noiopad
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select -assert-count 1 t:RAMB18E1
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# w32b | r4b
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design -reset
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read_verilog asym_ram_sdp_write_wider.v
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chparam -set WIDTHA 32 -set SIZEA 128 -set ADDRWIDTHA 7 asym_ram_sdp_read_wider
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synth_xilinx -top asym_ram_sdp_write_wider -noiopad
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select -assert-count 1 t:RAMB18E1
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# w4b | r24b
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design -reset
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read_verilog asym_ram_sdp_read_wider.v
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chparam -set SIZEA 768
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chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
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synth_xilinx -top asym_ram_sdp_read_wider -noiopad
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select -assert-count 1 t:RAMB18E1
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