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044ca9dde4
This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
33 lines
1,008 B
Text
33 lines
1,008 B
Text
# Check that basic macro expansions do what you'd expect
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read_verilog <<EOT
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`define empty_arglist() 123
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`define one_arg(x) 123+x
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`define opt_arg(x = 1) 123+x
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`define two_args(x, y = (1+23)) x+y
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`define nested_comma(x = {31'b0, 1'b1}, y=3) x+y
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module top;
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localparam a = `empty_arglist();
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localparam b = `one_arg(10);
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localparam c = `opt_arg(10);
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localparam d = `opt_arg();
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localparam e = `two_args(1,2);
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localparam f = `two_args(1);
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localparam g = `nested_comma(1, 2);
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localparam h = `nested_comma({31'b0, (1'b0)});
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localparam i = `nested_comma(, 1);
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generate
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if (a != 123) $error("a bad");
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if (b != 133) $error("b bad");
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if (c != 133) $error("c bad");
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if (d != 124) $error("d bad");
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if (e != 3) $error("e bad");
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if (f != 25) $error("f bad");
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if (g != 3) $error("g bad");
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if (h != 3) $error("h bad");
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if (i != 2) $error("i bad");
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endgenerate
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endmodule
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EOT
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