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Code Activity
yosys/frontends
History
Emil J. Tywoniak 3a5f5c77bf twine: avoid TwinePool::lookup
2026-06-16 22:57:13 +02:00
..
aiger WIP 2026-06-12 16:25:07 +02:00
aiger2 WIP 2026-06-12 00:18:53 +02:00
ast twine: avoid TwinePool::lookup 2026-06-16 22:57:13 +02:00
blif twine: avoid TwinePool::lookup 2026-06-16 22:57:13 +02:00
json WIP 2026-06-12 00:18:53 +02:00
liberty WIP 2026-06-12 00:18:53 +02:00
rpc WIP 2026-06-12 00:18:53 +02:00
rtlil twine: avoid TwinePool::lookup 2026-06-16 22:57:13 +02:00
verific rtlil: set Module::design before name at all construction sites 2026-06-10 14:54:39 +02:00
verilog Support positional assignment patterns for unpacked arrays 2026-04-23 14:29:38 -07:00