mirror of
https://github.com/YosysHQ/yosys
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57 lines
1.4 KiB
Text
57 lines
1.4 KiB
Text
read_verilog <<EOF
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module top(
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input [1:0] a,
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input [2:0] b,
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output [2:0] y,
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input [2:0] a2,
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input [3:0] b2,
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output [3:0] y2,
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input [1:0] a3,
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input [2:0] b3,
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output [2:0] y3
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);
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assign y = a | (*keep*) b;
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assign y2 = a2 | (*keep*) b2;
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assign y3 = a3 | (*keep*) b3;
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endmodule
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EOF
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wreduce
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wrapcell -setattr foo -formatattr bar w{Y_WIDTH} -name OR_{A_WIDTH}_{B_WIDTH}_{Y_WIDTH}
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check -assert
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select -assert-count 2 top/t:OR_2_3_3
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select -assert-count 1 top/t:OR_3_4_4
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select -assert-none top/t:OR_2_3_3 top/t:OR_3_4_4 %% top/t:* %D
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select -assert-mod-count 2 OR_2_3_3 OR_3_4_4
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select -assert-mod-count 2 A:bar=w3 A:bar=w4
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design -reset
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read_verilog <<EOF
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module top(
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input [1:0] a,
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input [2:0] b,
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output [2:0] y,
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input [2:0] a2,
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input [3:0] b2,
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output [3:0] y2,
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input [1:0] a3,
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input [2:0] b3,
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output [2:0] y3
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);
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assign y = a | (*keep*) b;
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assign y2 = a2 | (*keep*) b2;
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wire [2:0] y3_ = a3 | (*keep*) b3;
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assign y3 = {y3_[2], y3_[0]};
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endmodule
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EOF
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opt_clean -unusedbitsattr
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wreduce
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wrapcell -setattr foo -formatattr bar w{Y_WIDTH} -name OR_{A_WIDTH}_{B_WIDTH}_{Y_WIDTH}{%unused}
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check -assert
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select -assert-count 1 top/t:OR_2_3_3
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select -assert-count 1 top/t:OR_2_3_3_unused_Y[1]
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select -assert-count 1 top/t:OR_3_4_4
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select -assert-none top/t:OR_2_3_3 top/t:OR_3_4_4 top/t:OR_2_3_3_unused_Y[1] %% top/t:* %D
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select -assert-mod-count 2 OR_2_3_3 OR_3_4_4
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select -assert-mod-count 3 A:bar=w3 A:bar=w4
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