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24 lines
406 B
Verilog
24 lines
406 B
Verilog
module example (
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input clk,
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input SW1,
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input SW2,
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output LED1,
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output LED2,
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output LED3,
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output LED4
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);
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localparam BITS = 4;
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localparam LOG2DELAY = 22;
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reg [BITS+LOG2DELAY-1:0] counter = 0;
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reg [BITS-1:0] outcnt;
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always @(posedge clk) begin
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counter <= counter + SW1 + SW2 + 1;
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outcnt <= counter >> LOG2DELAY;
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end
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assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
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endmodule
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