mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 09:34:09 +00:00
24b880b2de
Like wide port support, this is still completely unusable, and support in various passes will be gradually added later. It also has no support at all in the cell library, so attempting to create a read port with a reset or initial value will cause an assert failure for now.
93 lines
2.6 KiB
C++
93 lines
2.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef MEM_H
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#define MEM_H
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#include "kernel/yosys.h"
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#include "kernel/ffinit.h"
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YOSYS_NAMESPACE_BEGIN
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struct MemRd {
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bool removed;
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dict<IdString, Const> attributes;
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Cell *cell;
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int wide_log2;
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bool clk_enable, clk_polarity, ce_over_srst;
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Const arst_value, srst_value, init_value;
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bool transparent;
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SigSpec clk, en, arst, srst, addr, data;
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MemRd() : removed(false), cell(nullptr) {}
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};
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struct MemWr {
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bool removed;
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dict<IdString, Const> attributes;
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Cell *cell;
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int wide_log2;
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bool clk_enable, clk_polarity;
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std::vector<bool> priority_mask;
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SigSpec clk, en, addr, data;
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MemWr() : removed(false), cell(nullptr) {}
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};
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struct MemInit {
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dict<IdString, Const> attributes;
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Cell *cell;
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Const addr;
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Const data;
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MemInit() : cell(nullptr) {}
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};
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struct Mem {
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Module *module;
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IdString memid;
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dict<IdString, Const> attributes;
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bool packed;
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RTLIL::Memory *mem;
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Cell *cell;
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int width, start_offset, size;
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std::vector<MemInit> inits;
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std::vector<MemRd> rd_ports;
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std::vector<MemWr> wr_ports;
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void remove();
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void emit();
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void clear_inits();
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void check();
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Const get_init_data() const;
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static std::vector<Mem> get_all_memories(Module *module);
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static std::vector<Mem> get_selected_memories(Module *module);
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Cell *extract_rdff(int idx, FfInitVals *initvals);
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void narrow();
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// If write port idx2 currently has priority over write port idx1,
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// inserts extra logic on idx1's enable signal to disable writes
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// when idx2 is writing to the same address, then removes the priority
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// from the priority mask.
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void emulate_priority(int idx1, int idx2);
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Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}
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};
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YOSYS_NAMESPACE_END
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#endif
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