mirror of
https://github.com/YosysHQ/yosys
synced 2026-02-07 09:42:16 +00:00
2468b391bf
Currently when `s1` and `s2` are different bits of the same wire, it is possible for both `compare_signals(s1, s2)` and `compare_signals(s2, s1)` to return false. This means the calling code will call `assign_map.add()` for both `s1` and `s2`, which doesn't make much sense --- one of `s1` or `s2` should be consistently preferred. So fix that by preferring the `SigBit` with the smaller bit offset. |
||
|---|---|---|
| .. | ||
| cmds | ||
| equiv | ||
| fsm | ||
| hierarchy | ||
| memory | ||
| opt | ||
| pmgen | ||
| proc | ||
| sat | ||
| techmap | ||
| tests | ||