yosys/tests/errors/syntax_err01.v at 242ae4ef017a60c0e9231ed466e0431fc43dcfc9 - mirrors/yosys - Libre-Chip.org

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Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.

2018-10-25 02:37:56 +03:00

5 lines

38 B

Verilog

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 module a;
 integer [31:0]w;
 endmodule