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https://github.com/YosysHQ/yosys
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331ac5285f
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions. |
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| .. | ||
| .gitignore | ||
| alu.v | ||
| asserts.v | ||
| asserts.ys | ||
| asserts_seq.v | ||
| asserts_seq.ys | ||
| bug2595.ys | ||
| clk2fflogic.ys | ||
| counters-repeat.v | ||
| counters-repeat.ys | ||
| counters.v | ||
| counters.ys | ||
| dff.ys | ||
| expose_dff.v | ||
| expose_dff.ys | ||
| grom.ys | ||
| grom_computer.v | ||
| grom_cpu.v | ||
| initval.v | ||
| initval.ys | ||
| ram_memory.v | ||
| run-test.sh | ||
| share.v | ||
| share.ys | ||
| sim_counter.ys | ||
| sizebits.sv | ||
| sizebits.ys | ||
| splice.v | ||
| splice.ys | ||