Emil J 5f8489d36d Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors ... equiv_induct: error on missing model		2026-02-25 15:39:31 +01:00
..
dynamic_part_select
.gitignore	Add test for ezCmdlineSAT	2026-01-20 09:28:00 -08:00
abc9.v
abc9.ys
abstract_init.ys
abstract_initstates.ys
abstract_state.ys
abstract_value.ys
aiger2.ys
aiger_dff.ys
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys	Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.	2019-06-04 10:42:42 +02:00
attrib07_func_call.v
attrib07_func_call.ys
autoname.ys
blackbox_wb.ys
box_derive.ys
bufnorm_opt_clean.ys
bug1496.ys
bug1531.ys
bug1614.ys
bug1710.ys
bug1745.ys
bug1781.ys
bug1876.ys
bug2014.ys
bug3462.ys
bug3515.v	tests: Add bug3515	2025-11-25 07:04:34 +13:00
bug3515.ys	tests: Tidy up bug3515	2025-11-25 07:35:19 +13:00
bug3879.ys
bug4082.ys
bug4865.ys
bug4909.ys
cellarray_array_connections.ys
celledges_shift.ys
check.ys
check_2.ys
check_3.ys
check_4.ys
chformal_check.ys
chformal_coverenable.ys
chparam.sh
clk2fflogic_effects.sh
clk2fflogic_effects.sv
const_arg_loop.sv
const_arg_loop.ys
const_func.sv
const_func.ys
const_func_block_var.v
const_func_block_var.ys
const_shift_empty_arg.ys	Fix segfault from shift with 0-width signed arg.	2026-02-12 22:03:42 -06:00
constant_drive_conflict.ys
constcomment.ys
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
countbits.sv
countbits.ys
cutpoint_blackbox.ys
cutpoint_whole.ys
debugon.ys	Add -on/-off modes to debug pass	2026-01-15 12:07:26 -08:00
deminout_unused.ys
design.ys
design1.ys
design2.ys
design_equal_fail.ys	Implement design_equal command	2025-12-21 21:47:40 +00:00
design_equal_pass.ys	Implement design_equal command	2025-12-21 21:47:40 +00:00
dynamic_part_select.ys
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_assume.ys
equiv_make_make_assert.ys
equiv_opt_multiclock.ys
equiv_opt_undef.ys
exec.ys
ezcmdline_dummy_solver	Add test for ezCmdlineSAT	2026-01-20 09:28:00 -08:00
ezcmdline_plugin.cc	Add test for ezCmdlineSAT	2026-01-20 09:28:00 -08:00
ezcmdline_plugin.sh	Mimic pattern of how other tests build plugins	2026-01-20 10:44:47 -08:00
fib.v
fib.ys
fib_tern.v
fib_tern.ys
formalff_declockgate.ys
fsm-arst.ys	typo	2025-11-14 13:34:58 +02:00
func_port_implied_dir.sv
func_port_implied_dir.ys
gen_if_null.v
gen_if_null.ys
global_scope.ys
gzip_verilog.v.gz
gzip_verilog.ys
help.ys
hierarchy.sh
hierarchy_defer.ys
hierarchy_generate.ys
hierarchy_param.ys
ice40_mince_abc9.ys
integer_range_bad_syntax.ys
integer_real_bad_syntax.ys
json_escape_chars.ys
json_param_defaults.v	Add tests	2026-02-11 08:10:57 -08:00
json_param_defaults.ys	Don't dump params by default	2026-02-11 08:33:39 -08:00
json_scopeinfo.ys
keep_hierarchy.ys
lcov.gold
lcov.v
lcov.ys
logger_cmd_error.sh
logger_error.ys
logger_fail.sh
logger_nowarning.ys
logger_warn.ys
logger_warning.ys
logic_param_simple.ys
mem2reg.ys
memory_word_as_index.data
memory_word_as_index.v
memory_word_as_index.ys
muxcover.ys
muxpack.v
muxpack.ys
param_struct.ys
peepopt.ys
peepopt_formal.ys
plugin.cc
plugin.sh
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys
port_sign_extend.v
port_sign_extend.ys
primitives.ys
printattr.ys
rand_const.sv
rand_const.ys
reg_wire_error.sv
reg_wire_error.ys
rename_scramble_name.ys
rename_unescape.ys
rename_wire_move_to_cell.ys
rtlil_signed_attribute.ys
rtlil_z_bits.ys
run-test.sh
scopeinfo.ys
scratchpad.ys
script.ys
setundef.sv
setundef.ys
sformatf.ys
shregmap.v
shregmap.ys
signed.ys
signext.ys
sim_const.ys
specify.v
specify.ys	specify: fix test	2026-02-03 18:40:32 +01:00
splitnets.ys
src.ys
sta.ys
stat.ys
stat_area_by_width.lib
stat_hierarchy.ys
stat_high_level.ys
stat_high_level2.ys
struct_access.sv
struct_access.ys
sub.v
submod.ys
submod_extract.ys
sv_defines.ys
sv_defines_dup.ys
sv_defines_mismatch.ys
sv_defines_too_few.ys
sv_implicit_ports.sh
svalways.sh
tcl_apis.tcl
tcl_apis.v
tcl_apis.ys
timeest.ys	timeest: Add top ports launching/sampling	2025-11-03 14:21:28 +01:00
wrapcell.ys
wreduce.ys
wreduce2.ys
write_gzip.ys
xaiger.ys