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yosys/tests/arch
Krystine Sherwin 5d3ed5a418 analogdevices: Extra tests
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
2026-03-05 05:37:13 +00:00
..
analogdevices analogdevices: Extra tests 2026-03-05 05:37:13 +00:00
anlogic
common analogdevices: Extra tests 2026-03-05 05:37:13 +00:00
ecp5
efinix
fabulous
gatemate
gowin
ice40
intel_alm
machxo2
microchip
nanoxplore
nexus
quicklogic
xilinx
run-test.sh