Emil J. Tywoniak 9c3704d5a4 cxxrtl: ignore $input_port		2026-07-17 23:33:02 +02:00
..
aiger	aiger: ignore $input_port	2026-07-17 23:33:02 +02:00
aiger2
blif
btor
cxxrtl	cxxrtl: ignore $input_port	2026-07-17 23:33:02 +02:00
edif
firrtl
functional	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
intersynth
jny
json
rtlil
simplec
smt2	yosys-witness: give error on justice property, support only 'b'	2026-07-07 12:19:38 +02:00
smv
spice
table
verilog
CMakeLists.txt