mirror of
https://github.com/YosysHQ/yosys
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18 lines
653 B
Python
18 lines
653 B
Python
from pathlib import Path
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from pyosys import libyosys as ys
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__file_dir__ = Path(__file__).absolute().parent
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add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v"
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base = ys.Design()
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ys.run_pass(f"read_verilog {add_sub}", base)
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ys.run_pass("hierarchy -top top", base)
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ys.run_pass("proc", base)
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ys.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5", base)
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postopt = ys.Design()
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ys.run_pass("design -load postopt", postopt)
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ys.run_pass("cd top", postopt)
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ys.run_pass("select -assert-min 11 t:LUT4", postopt)
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ys.run_pass("select -assert-count 2 t:PFUMX", postopt)
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ys.run_pass("select -assert-none t:LUT4 t:PFUMX %% t:* %D", postopt)
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