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mirror of https://github.com/YosysHQ/yosys synced 2025-10-27 01:39:23 +00:00
Code Activity
yosys/frontends
History
Clifford Wolf 1276c87a56 Added read_verilog -norestrict -assume-asserts
2016-08-26 23:35:27 +02:00
..
ast Fixed bug with memories that do not have a down-to-zero data width 2016-08-22 14:27:46 +02:00
blif Added "read_blif -sop" 2016-06-18 12:33:13 +02:00
ilang Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
liberty Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
verific Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
verilog Added read_verilog -norestrict -assume-asserts 2016-08-26 23:35:27 +02:00
vhdl2verilog Added "yosys -D" feature 2016-04-21 23:28:37 +02:00