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yosys/docs/source/code_examples/opt/opt_merge.ys
Miodrag Milanovic 48a3dcc02a End of file fix
2026-06-23 07:23:41 +02:00

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Text

read_verilog <<EOT
module uut(
input [3:0] a, b,
output [3:0] y, z
);
assign y = a + b;
assign z = b + a;
endmodule
EOT
copy uut after
opt_merge after
clean
show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut