3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-26 18:48:51 +00:00
yosys/tests/sim/simple_assign.vcd
Miodrag Milanovic 48a3dcc02a End of file fix
2026-06-23 07:23:41 +02:00

13 lines
169 B
Text

$version Yosys $end
$scope module simple_assign $end
$var wire 1 n2 in $end
$var wire 1 n1 out $end
$upscope $end
$enddefinitions $end
#0
#5
b1 n1
b1 n2
#10
b0 n1
b0 n2