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yosys/docs/source/using_yosys/synthesis
History
Krystine Sherwin e40134c856
Docs: Update for properties 
Add properties page, move cell_gate and cell_word under a singular cell_index along with properties.  Fix links accordingly.

Also drop x-aware and x-output todos since they are resolved.
2024-10-15 07:35:41 +13:00
..
abc.rst Docs: Reflow line length 2024-10-15 07:23:45 +13:00
cell_libs.rst Docs: Reflow line length 2024-10-15 07:23:45 +13:00
extract.rst Docs: Reflow line length 2024-10-15 07:23:45 +13:00
fsm.rst Docs: Less leading backslashes 2024-10-15 07:34:52 +13:00
index.rst Docs: Reflow line length 2024-10-15 07:23:45 +13:00
memory.rst Docs: Reflow line length 2024-10-15 07:23:45 +13:00
opt.rst Docs: Update for properties 2024-10-15 07:35:41 +13:00
proc.rst Docs: Reflow line length 2024-10-15 07:23:45 +13:00
synth.rst Docs: Shorten cmd:ref 2024-10-15 07:22:04 +13:00
techmap_synth.rst Docs: Fix invalid autorefs 2024-10-15 07:34:53 +13:00