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2021ddecb3
yosys
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techlibs
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altera_intel
History
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
..
cycloneiv
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
max10
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
lpm_functions.v
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
Makefile.inc
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
2017-04-05 23:01:29 -05:00
synth_intel.cc
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00