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yosys/tests
2020-02-05 16:41:09 -08:00
..
aiger Add testcases 2020-01-07 11:44:20 -08:00
arch Merge pull request #1650 from YosysHQ/eddie/shiftx2mux 2020-02-05 14:55:57 -08:00
asicworld
bram
errors
fsm Speed up "make test" and related cleanups 2019-08-17 14:37:07 +02:00
hana
liberty
lut
memories
opt Merge pull request #1576 from YosysHQ/eddie/opt_merge_init 2020-02-05 14:56:26 -08:00
opt_share
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
realmath
rpc rpc: new frontend. 2019-09-30 15:53:11 +00:00
sat Merge pull request #1638 from YosysHQ/eddie/fix1631 2020-02-05 19:31:18 +01:00
share
simple Make SV2017 compliant courtesy of @wsnyder 2019-12-12 07:34:07 -08:00
simple_abc9 simple_abc9 tests to discard whitebox before write for sim 2020-01-23 22:07:43 -08:00
smv
sva
svinterfaces
svtypes Use "(id)" instead of "id" for types as temporary hack 2019-10-14 05:24:31 +02:00
techmap shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
tools
unit
various sv: More tests for wildcard port connections 2020-02-02 16:12:33 +00:00
vloghtb