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yosys/backends
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Sahand Kashani 1f1b64b880 Add extmodule support to firrtl backend 
The current firrtl backend emits blackboxes as standard modules
with an empty body, but this causes the firrtl compiler to
optimize out entire circuits due to the absence of any drivers.

Yosys already tags blackboxes with a (*blackbox*) attribute, so this
commit just propagates this change to firrtl's syntax for blackboxes.
2020-05-06 01:01:14 +02:00
..
aiger aiger: fixes for ports that have start_offset != 0 2020-05-02 10:00:32 -07:00
blif kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
btor kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
cxxrtl cxxrtl: Round up constant width 2020-04-25 10:42:21 +01:00
edif Improve net priorities in EDIF back-end 2020-04-21 12:35:25 +02:00
firrtl Add extmodule support to firrtl backend 2020-05-06 01:01:14 +02:00
ilang ilang, ast: Store parameter order and default value information. 2020-04-21 19:09:00 +02:00
intersynth Clean up pseudo-private member usage in backends/intersynth/intersynth.cc. 2020-04-01 06:32:09 +00:00
json write_json: dump default parameter values 2020-04-21 19:09:00 +02:00
protobuf Add aiger and protobuf backends binary support 2019-09-28 09:51:48 +02:00
simplec kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
smt2 Merge pull request #1830 from boqwxp/qbfsat 2020-04-15 17:33:50 +02:00
smv kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
spice kernel: use more ID::* 2020-04-02 07:14:08 -07:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog write_verilog: fix precondition check. 2020-04-14 12:12:50 +00:00