mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
4 lines
74 B
Verilog
4 lines
74 B
Verilog
module cmos_demo(input a, b, output [1:0] y);
|
|
assign y = a + b;
|
|
endmodule
|