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59 lines
2.5 KiB
ReStructuredText
59 lines
2.5 KiB
ReStructuredText
Internal formats
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Yosys uses two different internal formats. The first is used to store an
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abstract syntax tree (AST) of a Verilog input file. This format is simply called
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AST and is generated by the Verilog Frontend. This data structure is consumed by
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a subsystem called AST Frontend [1]_. This AST Frontend then generates a design
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in Yosys' main internal format, the
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Register-Transfer-Level-Intermediate-Language (RTLIL) representation. It does
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that by first performing a number of simplifications within the AST
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representation and then generating RTLIL from the simplified AST data structure.
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The RTLIL representation is used by all passes as input and outputs. This has
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the following advantages over using different representational formats between
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different passes:
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- The passes can be rearranged in a different order and passes can be removed
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or inserted.
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- Passes can simply pass-thru the parts of the design they don't change without
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the need to convert between formats. In fact Yosys passes output the same
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data structure they received as input and performs all changes in place.
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- All passes use the same interface, thus reducing the effort required to
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understand a pass when reading the Yosys source code, e.g. when adding
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additional features.
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The RTLIL representation is basically a netlist representation with the
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following additional features:
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- An internal cell library with fixed-function cells to represent RTL datapath
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and register cells as well as logical gate-level cells (single-bit gates and
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registers).
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- Support for multi-bit values that can use individual bits from wires as well
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as constant bits to represent coarse-grain netlists.
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- Support for basic behavioural constructs (if-then-else structures and
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multi-case switches with a sensitivity list for updating the outputs).
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- Support for multi-port memories.
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The use of RTLIL also has the disadvantage of having a very powerful format
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between all passes, even when doing gate-level synthesis where the more advanced
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features are not needed. In order to reduce complexity for passes that operate
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on a low-level representation, these passes check the features used in the input
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RTLIL and fail to run when unsupported high-level constructs are used. In such
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cases a pass that transforms the higher-level constructs to lower-level
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constructs must be called from the synthesis script first.
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.. toctree::
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:maxdepth: 3
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rtlil_rep
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.. [1]
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In Yosys the term pass is only used to refer to commands that operate on the
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RTLIL data structure.
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