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arith_map.v
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Use HTTPS for website links, gatecat email
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2021-06-09 12:16:56 +02:00 |
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brams.txt
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nexus: Add make_transp to BRAMs
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2020-10-22 15:11:59 +01:00 |
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brams_init.vh
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synth_nexus: Initial implementation
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2020-10-15 08:52:15 +01:00 |
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brams_map.v
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synth_nexus: Initial implementation
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2020-10-15 08:52:15 +01:00 |
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cells_map.v
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Gowin: deal with active-low tristate (#2971)
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2021-08-20 21:21:06 +02:00 |
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cells_sim.v
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nexus: Add MULTADDSUB9X9WIDE sim model
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2020-12-08 15:49:20 +00:00 |
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cells_xtra.py
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nexus: Add DSP simulation model
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2020-11-18 10:21:17 +00:00 |
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cells_xtra.v
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nexus: Add DSP simulation model
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2020-11-18 10:21:17 +00:00 |
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dsp_map.v
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nexus: DSP inference support
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2020-11-20 08:45:55 +00:00 |
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latches_map.v
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synth_nexus: Initial implementation
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2020-10-15 08:52:15 +01:00 |
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lrams.txt
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nexus: Add LRAM inference
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2020-12-07 13:27:17 +00:00 |
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lrams_init.vh
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nexus: Add LRAM inference
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2020-12-07 13:27:17 +00:00 |
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lrams_map.v
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nexus: Add LRAM inference
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2020-12-07 13:27:17 +00:00 |
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lutrams.txt
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synth_nexus: Initial implementation
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2020-10-15 08:52:15 +01:00 |
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lutrams_map.v
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synth_nexus: Initial implementation
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2020-10-15 08:52:15 +01:00 |
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Makefile.inc
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nexus: Add LRAM inference
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2020-12-07 13:27:17 +00:00 |
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parse_init.vh
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synth_nexus: Initial implementation
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2020-10-15 08:52:15 +01:00 |
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synth_nexus.cc
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Use HTTPS for website links, gatecat email
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2021-06-09 12:16:56 +02:00 |
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