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24 lines
444 B
Verilog
24 lines
444 B
Verilog
module carryadd(a, b, y);
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parameter WIDTH = 8;
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input [WIDTH-1:0] a, b;
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output [WIDTH-1:0] y;
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genvar i;
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generate
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for (i = 0; i < WIDTH; i = i+1) begin:STAGE
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wire IN1 = a[i], IN2 = b[i];
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wire C, Y;
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if (i == 0)
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assign C = IN1 & IN2, Y = IN1 ^ IN2;
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else
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assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE[i-1].C),
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Y = IN1 ^ IN2 ^ STAGE[i-1].C;
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assign y[i] = Y;
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end
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endgenerate
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// assert property (y == a + b);
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endmodule
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