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34 lines
464 B
Text
34 lines
464 B
Text
read_verilog << EOT
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module top(...);
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input clk;
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input [3:0] wa;
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input [15:0] wd;
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input [3:0] ra;
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output [15:0] rd;
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reg [15:0] mem[0:15];
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integer i;
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reg x;
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always @(posedge clk) begin
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for (i = 0; i < 2; i = i + 1) begin
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x = i == 1;
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if (x)
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mem[wa] <= wd;
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end
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end
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assign rd = mem[ra];
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endmodule
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EOT
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proc
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opt
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select -assert-count 2 t:$memwr_v2
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opt_mem
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select -assert-count 1 t:$memwr_v2
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