mirror of
https://github.com/YosysHQ/yosys
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107 lines
3.6 KiB
C++
107 lines
3.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptMemWidenPass : public Pass {
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OptMemWidenPass() : Pass("opt_mem_widen", "optimize memories where all ports are wide") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_mem_widen [options] [selection]\n");
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log("\n");
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log("This pass looks for memories where all ports are wide and adjusts the base\n");
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log("memory width up until that stops being the case.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// if (args[argidx] == "-nomux") {
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// mode_nomux = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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for (auto &mem : Mem::get_selected_memories(module)) {
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// If the memory has no read ports, opt_clean will remove it
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// instead.
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if (mem.rd_ports.empty())
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continue;
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int factor_log2 = mem.rd_ports[0].wide_log2;
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for (auto &port : mem.rd_ports)
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if (port.wide_log2 < factor_log2)
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factor_log2 = port.wide_log2;
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for (auto &port : mem.wr_ports)
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if (port.wide_log2 < factor_log2)
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factor_log2 = port.wide_log2;
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if (factor_log2 == 0)
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continue;
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log("Widening base width of memory %s in module %s by factor %d.\n", log_id(mem.memid), log_id(module->name), 1 << factor_log2);
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total_count++;
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// The inits are too messy to expand one-by-one, for they may
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// collide with one another after expansion. Just hit it with
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// a hammer.
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bool has_init = !mem.inits.empty();
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Const init_data;
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if (has_init) {
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init_data = mem.get_init_data();
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mem.clear_inits();
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}
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mem.width <<= factor_log2;
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mem.size >>= factor_log2;
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mem.start_offset >>= factor_log2;
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if (has_init) {
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MemInit new_init;
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new_init.addr = mem.start_offset;
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new_init.data = init_data;
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new_init.en = Const(State::S1, mem.width);
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mem.inits.push_back(new_init);
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}
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for (auto &port : mem.rd_ports) {
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port.wide_log2 -= factor_log2;
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port.addr = port.addr.extract_end(factor_log2);
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}
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for (auto &port : mem.wr_ports) {
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port.wide_log2 -= factor_log2;
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port.addr = port.addr.extract_end(factor_log2);
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}
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mem.emit();
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}
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}
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if (total_count)
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design->scratchpad_set_bool("opt.did_something", true);
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log("Performed a total of %d transformations.\n", total_count);
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}
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} OptMemWidenPass;
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PRIVATE_NAMESPACE_END
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